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Implementation of Low Power High Speed 16-Bit Approximate Multiplier for DSP Applications

. M. Mahesh


 In many of the applications or packages, we do not require accurate results, like records processing and virtual signal processing that is message or data are packed together to achieve the desired result. Therefore, by using the layout of multiplier, we can consume speed of the process and power used by the processor, but multiplier effects a large area on the delay and energy intake on mathematical functions especially on the arithmetic processor. The parameters like speed and power can be covered by the use of an approximate multiplier. This paper has been designed for a 16-bit approximate multiplier. The complexities of the addition of those partial distributions are reduced based on the possibility. The proposed multiplier gains greater velocity and power consumption in comparison to the previous particular multiplier have seen in the synthesis results. Keywords: Accurate process, compressors, product multiplier 

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