The discrete Hartley transform is a real valued transform, comparable to the complex Fourier transform, which has many applications in disciplines such as pattern recognition, signal and image processing. In this paper, a new very large scale integration VLSI algorithm for an 8 point discrete Hartley transform DHT is presented, named as Dual group adaptive DHT algorithm which can be efficiently implemented on a highly modular and parallel VLSI architecture with a regular structure and consists of two blocks: a multiplication block and an addition subtraction block. The proposed DHT algorithm may be efficiently divided into many parallel components that can be run concurrently. Furthermore, the proposed algorithm lends itself well to the sharing approach, which may be utilised to greatly decrease the hardware complexity of a highly parallel VLSI implementation. The proposed architecture employs only two multipliers and 36 adders. Using the benefits of the proposed algorithm, the number of multipliers has been considerably decreased, resulting in a very small number of multipliers when compared to the existing algorithms. Furthermore, constant multipliers can be effectively implemented in VLSI. As a result, the proposed design is an effective solution for space constrained applications.
Keywords - Discrete Hartley Transform, Multiplier, Adder, Real-valued Transform, VLSI, Systolic arrays